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general description the max9396 consists of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. the multiplexer section (channel b) accepts two differential inputs and gener- ates a single differential output. the demultiplexer sec- tion (channel a) accepts a single differential input and generates two parallel differential outputs. the max9396 features a loopback mode that connects the input of channel a to the output of channel b and con- nects the selected input of channel b to the outputs of channel a. the differential inputs of the max9396 accept cml/lvpecl levels and can also accept lvds inputs with common-mode voltages from +0.6v to (v cc - 0.05v). the differential outputs are lvds compatible and drive 100 ? loads. three lvcmos/lvttl logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel b (bsel), and the other two for loopback control of channels a and b (lb_sela and lb_selb). independent enable inputs for each dif- ferential output pair provide additional flexibility. fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common- mode voltage is below +0.6v. ultra-low 57ps p-p (typ) pseudorandom bit sequence (prbs) jitter ensures reliable communications in high- speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. the high-speed switch- ing performance guarantees 1.25gbps operation and less than 87ps (max) skew between channels. the max9396 is available in a 32-pin tqfp package and is specified over the -40? to +85? extended tem- perature range. applications high-speed telecom/datacom equipment central office backplane clock distribution dslams protection switching fault-tolerant systems features ? guaranteed 1.25gbps operation with 450mv (min) differential output swing ? integrated 100 ? resistors on differential inputs ? simultaneous loopback control ? 2ps (rms) (max) random jitter ? ac specifications guaranteed for 150mv differential input ? signal inputs accept any differential signals with v cm = +0.6v to (v cc - 0.05v) ? lvds outputs for clock or high-speed data ? low-level input fail-safe detection ? +3.0v to +3.6v supply voltage range ? lvcmos/lvttl logic inputs max9396 2:1 multiplexer and 1:2 demultiplexer with loopback ________________________________________________________________ maxim integrated products 1 ordering information 0.1 f 0.01 f +3.0v to +3.6v outa0 outa0 lvds receiver ina ina ena0 ena1 enb gnd gnd gnd gnd outa1 outa1 outb outb lvcmos/lvttl logic inputs lb_sela lb_selb bsel inb0 inb0 z 0 = 50 ? z 0 = 50 ? max9396 v cc inb1 inb1 z 0 = 50 ? z 0 = 50 ? 100 ? z 0 = 50 ? z 0 = 50 ? z 0 = 50 ? z 0 = 50 ? typical operating circuit 19-0736; rev 0; 1/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code max9396ehj+ -40? to +85? 32 tqfp h32-1 + denotes a lead-free package. pin configuration and functional diagram appear at end of data sheet.
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................-0.3v to +4.1v in_ _, in _ _, out_ _, out _ _, en_ _, bsel, lb_sel_ to gnd....................................................-0.3v to (v cc + 0.3v) in_ _ to in _ _..........................................................................?v short-circuit duration (out_ _, out _ _) ...................continuous continuous power dissipation (t a = +70?) 32-pin tqfp (derate 13.1mw/? above +70?)........1047mw junction-to-ambient thermal resistance in still air 32-pin tqfp............................................................+76.4?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection (human body model) (in_ _, in _ _, out_ _, out _ _, en_ _, bsel, lb_sel_)..?kv lead temperature (soldering, 10s) .................................+300? dc electrical characteristics (v cc = +3.0v to +3.6v, r l = 100 ? ?%, en_ _ = v cc , v cm = +0.6v to (v cc - 0.05v), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.2v, t a = +25?.) (notes 1, 2, and 3) parameter sym b o l conditions min typ max units lvcmos/lvttl inputs (en_ _, bsel, lb_sel_) input high voltage v ih 2.0 v cc v input low voltage v il 0 0.8 v input high current i ih v in = +2.0v to v cc 020a input low current i il v in = 0v to +0.8v -1 +10 ? differential inputs (in_ _, in _ _) differential input voltage v id v ild > 0v and v ihd < v cc , figure 1 0.1 3.0 v input common-mode range v cm 0.6 v cc - 0.05 v single-ended input current i in_ _ , i in _ _ |v id | 3.0v (v in = 0v to +v cc , in_ _, or in _ _ open) -15 +200 ? differential input termination r in in_ _ to in _ _80 100 120 ? lvds outputs (out_ _, out _ _) differential output voltage v od r l = 100 ? , figure 2 450 540 600 mv change in magnitude of v od between complementary output states ? v od figure 2 50 mv offset common-mode voltage v os figure 2 1.4 1.5 1.6 v change in magnitude of v os between complementary output states ? v os figure 2 50 mv
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback _______________________________________________________________________________________ 3 parameter sym b o l conditions min typ max units v out_ _ or v out _ _ = 0v 28 40 output short-circuit current (output(s) shorted to gnd) |i os | v id = 100mv (note 4) v out_ _ = v out _ _ = 0v 17 24 ma output short-circuit current (outputs shorted together) |i osb | v id = 100mv, v out_ _ = v out _ _ (note 4) 12 ma supply current r l = 100 ? , en_ _ = v cc 56 75 supply current i cc r l = 100 ? , en_ _ = v cc , switching at 625mhz (1.25gbps) 56 75 ma note 1: measurements obtained with the device in thermal equilibrium. all voltages referenced to gnd except v id , v od , and ? v od . note 2: current into the device defined as positive. current out of the device defined as negative. note 3: dc parameters are production tested at t a = +25? and guaranteed by design and characterization for t a = -40? to +85?. note 4: current through either output. note 5: guaranteed by design and characterization. limits set at ? sigma. note 6: t skew is the magnitude difference of differential propagation delays for the same output over the same condtions. t skew = |t phl - t plh |. note 7: measured between outputs of the same device at the signal crossing points for a same-edge transition under the same con- ditions. does not apply to loopback mode. note 8: device jitter added to the differential input signal. dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, r l = 100 ? ?%, en_ _ = v cc , v cm = +0.6v to (v cc - 0.05v), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.2v, t a = +25?.) (notes 1, 2, and 3) ac electrical characteristics (v cc = +3.0v to +3.6v, f in 625mhz, t r_in = t f_in = 125ps, r l = 100 ? ?%, |v id | 150mv, v cm = +0.6v to (v cc - 0.075v), en_ _ = v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.2v, f in = 625mhz, t a = +25?.) (note 5) parameter sym b o l conditions min typ max units sel to switched output t switch figure 3 1.1 ns disable time to differential output low t phd figure 4 1.7 ns enable time to differential output high t pdh figure 4 1.7 ns data rate f dr v od > 450mv, 2 23 - 1 prbs 1.25 gbps low-to-high propagation delay t plh figures 1, 5 250 340 630 ps high-to-low propagation delay t phl figures 1, 5 250 355 630 ps pulse skew |t plh e t phl |t skew figures 1, 5 (note 6) 18 86 ps output channel-to-channel skew t ccs figure 6 (note 7) 87 ps output low-to-high transition time (20% to 80%) t r f in_ _ = 100mhz, figures 1, 5 170 220 350 ps output high-to-low transition time (80% to 20%) t f f in_ _ = 100mhz, figures 1, 5 170 210 350 ps added random jitter t rj f in_ _ = 625mhz, clock pattern (note 8) 0.45 2 ps (rms) added deterministic jitter t dj 1.25gbps, 2 23 - 1 prbs (note 8) 57 120 ps p-p
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, |v id | = 0.2v, v cm = +1.2v, t a = +25?, f in = 6.25mhz, figure 5.) supply current vs. temperature max9396 toc01 temperature ( c) supply current (ma) 60 35 -10 -15 45 50 55 60 65 70 40 -40 85 v cc = +3.6v v cc = +3.3v v cc = +3v output amplitude vs. frequency max9396 toc02 frequency (ghz) output amplitude (mv) 0.8 0.6 0.4 0.2 100 200 300 400 500 600 700 0 01.0 output rise/fall time vs. temperature max9396 toc03 temperature ( c) rise/fall time (ps) 60 35 10 -15 210 240 270 300 330 360 180 -40 85 f in = 100mhz t r t f propagation delay vs. temperature max9396 toc04 temperature ( c) propagation delay (ps) 60 35 -15 10 305 330 355 380 405 430 455 480 280 -40 85 t p hl t p lh single-ended input current vs. temperature max9396 toc05 temperature ( c) input current ( a) 60 35 -15 10 0 20 40 60 80 100 120 140 -20 -40 85 v in_ _ = 0v v in_ _ = v cc
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback _______________________________________________________________________________________ 5 pin description pin name function 1, 2, 3, 30, 31, 32 n.c. no connection. not internally connected. 4, 9, 20, 25 gnd ground 5 enb channel b output enable. drive enb high to enable the lvds outputs for channel b. an internal 435k ? resistor to gnd pulls enb low when unconnected. 6 outb channel b lvds noninverting output 7 outb channel b lvds inverting output 8, 13, 24, 29 v cc power-supply input. bypass each v cc to gnd with a 0.1? and 0.01? ceramic capacitor. install both bypass capacitors as close as possible to the device, with the 0.01? capacitor closest to the device. 10 inb0 lvpecl/cml inverting input. an internal 68k ? resistor to gnd pulls the input low when unconnected. 11 inb0 lvpecl/cml noninverting input. an internal 68k ? resistor to gnd pulls the input low when unconnected. 12 lb_selb loopback select for channel b output. connect lb_selb to gnd or leave unconnected to reproduce the inb_ ( inb_ ) differential inputs at outb ( outb ). connect lb_selb to v cc to loop back the ina ( ina ) differential inputs to outb ( outb ). an internal 435k ? resistor to gnd pulls lb_selb low when unconnected. 14 inb1 i i a ? resistor to gnd pulls the input low when unconnected. 15 inb1 lvpecl/cml noninverting input. an internal 68k ? resistor to gnd pulls the input low when unconnected. 16 bsel channel b multiplexer control input. selects the differential input to reproduce at the b channel differential output. connect bsel to gnd or leave unconnected to select the inb0 ( inb0 ) set of inputs. connect bsel to v cc to select the inb1 ( inb1 ) set of inputs. an internal 435k ? resistor to gnd pulls bsel low when unconnected. 17 ena1 channel a1 output enable. drive ena1 high to enable the a1 lvds outputs. an internal 435k ? resistor to gnd pulls the ena1 low when unconnected. 18 outa1 channel a1 lvds inverting output 19 outa1 channel a1 lvds noninverting output
max9396 detailed description the max9396 high-speed, low-power 2:1 multiplexer and 1:2 demultiplexer with loopback provides signal redundancy switching in telecom and storage applica- tions. this device selects one of two remote signal sources for local input and buffers a single local output signal to two remote receivers. the multiplexer section (channel b) accepts two differen- tial inputs and generates a single lvds-compatible out- put. the demultiplexer section (channel a) accepts a single differential input and generates two parallel lvds- compatible outputs. the max9396 features a loopback mode that connects the input of channel a to the output of channel b and connects the selected input of channel b to the outputs of channel a. lb_sela and lb_selb provide independent loopback control for each channel. three lvcmos/lvttl logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel b (bsel), and the other two for loopback control of channels a and b (lb_sela and lb_selb). independent enable inputs for each dif- ferential output pair provide additional flexibility. input fail-safe the differential inputs of the max9396 possess internal fail-safe protection. fail-safe circuitry forces the outputs to a differential-low condition for undriven inputs or when the common-mode voltage is below +0.6v. the max9396 provides low-level input fail-safe detection for lvpecl, cml, and other v cc -referenced differential inputs. select function bsel selects the differential input pair to transmit through outb ( outb ) for lb_selb = gnd or through outa_ ( outa_ ) for lb_sela = v cc . lb_sel_ controls the loopback function for each channel. connect lb_sel_ to gnd to select the normal inputs for each channel. connect lb_sel_ to v cc to enable the loop- back function. the loopback function routes the input of channel a to the output of channel b, and the inputs of channel b to the outputs of channel a. see tables 1 and 2 for a summary of the input/output routing between channels. 2:1 multiplexer and 1:2 demultiplexer with loopback 6 _______________________________________________________________________________________ pin description (continued) pin name function 21 ena0 channel a0 output enable. drive ena0 high to enable the a0 lvds outputs. an internal 435k ? resistor to gnd pulls ena0 low when unconnected. 22 outa0 channel a0 lvds inverting output 23 outa0 channel a0 lvds noninverting output 26 ina lvpecl/cml noninverting input. an internal 68k ? resistor to gnd pulls the input low when unconnected. 27 ina lvpecl/cml inverting input. an internal 68k ? resistor to gnd pulls the input low when unconnected. 28 lb_sela loopback select for channel a output. connect lb_sela to gnd or leave unconnected to reproduce the ina ( ina ) differential inputs at outa_ ( outa_ ). connect lb_sela to v cc to loop back the inb_ ( inb_ ) differential inputs to outa_ ( outa_ ). an internal 435k ? resistor to gnd pulls lb_sela low when unconnected.
enable function the en_ _ logic inputs enable and disable each set of differential outputs. for example, connect ena0 to v cc to enable the outa0/ outa0 differential output pair or connect ena0 to gnd to disable the outa0/ outa0 differential output pair. the differential output pairs assert to a differential low condition when disabled. applications information differential inputs the max9396 inputs accept any differential signaling standard within the specified common-mode voltage range. the fail-safe feature detects common-mode input signal levels and generates a differential output low condition for undriven inputs or when the common- mode voltage is below +0.6v. leave unused inputs unconnected or connect to gnd. power-supply bypassing bypass each v cc to gnd with high-frequency surface- mount ceramic 0.1? and 0.01? capacitors in parallel as close as possible to the device. install the 0.01? capacitor closest to the device. differential traces input and output trace characteristics affect the perfor- mance of the max9396. connect each input and output to a 50 ? characteristic impedance trace. maintain the distance between differential traces and eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode noise immu- nity. minimize the number of vias on the differential input and output traces to prevent impedance disconti- nuities. reduce reflections by maintaining the 50 ? characteristic impedance through connectors and across cables. minimize skew by matching the electri- cal length of the traces. output termination terminate the transmission line with a 100 ? resistor at the receiver inputs for proper operation. ensure that the output currents do not exceed the cur- rent limits specified in the absolute maximum ratings . observe the total thermal limits of the max9396 under all operating conditions. cables and connectors use matched differential impedance for transmission media. use cables and connectors with matched differ- ential impedance to minimize impedance discontinu- ities. avoid the use of unbalanced cables. balanced cables, such as twisted pair, offer superior signal quality and tend to generate less emi due to canceling effects. max9396 2:1 multiplexer and 1:2 demultiplexer with loopback _______________________________________________________________________________________ 7 t phl t plh 80% 20% 20% 80% 50% v od = 0v v od = 0v v id = 0v v od = 0v v od = 0v v id = 0v 50% v id = v in_ _ - v in_ _ v od = v out_ _ - v out_ _ v in_ _ v ihd v ild v in_ _ v out_ _ v out_ _ t f t r figure 1. output transition time and propagation delay timing diagram v id = v in_ _ - v in_ _ ? v od = ? v od - v od * ? r l = 100 ? 1% ? v os = ? v os - v os * ? v od and v os are measured with v id = +100mv. v od * and v os * are measured with v id = -100mv. in_ _ in_ _ r l /2 r l /2 22k ? 22k ? 100 ? v od out_ _ out_ _ max9396 en_ _ = high v os figure 2. test circuit for v od and v os
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback 8 _______________________________________________________________________________________ v ihd v ild v ihd v ild v ih v il t switch t switch inb0 inb0 inb1 inb1 v id = 0v v id = 0v bsel 1.5v inb1 out_ _ out_ _ en_0 = en_1 = high v id = v in_ _ - v in_ _ inb0 inb0 1.5v v od = 0v v od = 0v figure 3. input to rising/falling edge select and mux switch timing diagram v id = v in_ _ - v in_ _ 0v 3v 1.5v 1.5v v en_ _ t phd t phd t pdh t pdh 50% 50% 50% 50% v out_ _ when v id = +100mv v out_ _ when v id = -100mv c l pulse generator r l /2 r l /2 50 ? out_ _ out_ _ +1.25v c l v out_ _ when v id = -100mv v out_ _ when v id = +100mv en_ _ r l = 100 ? 1% c l = 1.0pf in_ _ in_ _ 22k ? 22k ? 100 ? max9396 figure 4. output active-to-disable and disable-to-active test circuit and timing diagram
pcb layout use a four-layer pcb providing separate signal, power, and ground planes for high-speed signaling applica- tions. bypass v cc to gnd as close as possible to the device. install termination resistors as close as possible to the receiver inputs. match the electrical length of the differential traces to minimize signal skew. max9396 2:1 multiplexer and 1:2 demultiplexer with loopback _______________________________________________________________________________________ 9 logic inputs differential outputs lb_sela lb_selb bsel outa_ / outa_ outb / outb 0 0 0 ina selected inb0 selected 0 0 1 ina selected inb1 selected 0 1 x ina selected ina selected 1 0 0 inb0 selected inb0 selected 1 0 1 inb1 selected inb1 selected 1 1 0 inb0 selected ina selected 1 1 1 inb1 selected ina selected table 1. input select truth table lb_sel_ out_ _ gnd or open normal inputs selected. v cc loopback inputs selected. table 2. loopback select truth table lb_sela 0 lb pulse generator outa0 outa0 outa1 outa1 c l r l r l ina ina c l c l c l ena0 = ena1 = high 1 channel shown. from channel b r l = 100 ? 1% c l = 1.0pf 22k ? 22k ? 100 ? 22k ? 22k ? max9396 figure 5. output transition time, propagation delay, and output channel-to-channel skew test circuit x = don? care.
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback 10 ______________________________________________________________________________________ v od = v out_ _ - v out_ _ v od = 0v t ccs v od = 0v v od = 0v v od = 0v t ccs v outa0 v outa0 v outa1 v outa1 figure 6. output channel-to-channel skew 0 lb lb 0 outa1 ena1 ena0 lb_sela bsel outa1 outa0 outa0 ina ina inb0 inb0 inb1 inb1 enb lb_selb outb outb 1 0 max9396 100 ? 22k ? 22k ? 22k ? 22k ? 22k ? 22k ? 100 ? 100 ? functional diagram
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback ______________________________________________________________________________________ 11 pin configuration chip information process: bicmos top view max9396 tqfp + 32 28 29 30 31 25 26 27 n.c. n.c. v cc lb_sela n.c. ina ina gnd 10 13 15 14 16 11 12 9 gnd inb0 inb0 lb_selb v cc inb1 inb1 bsel 17 18 19 20 21 22 23 outa0 24 v cc outa0 ena0 gnd outa1 outa1 ena1 2 3 4 5 6 7 8 v cc outb outb gnd n.c. n.c. 1 n.c. enb
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback 12 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32l tqfp, 5x5x01.0.eps b 1 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm
max9396 2:1 multiplexer and 1:2 demultiplexer with loopback maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) b 2 2 21-0110 package outline, 32l tqfp, 5x5x1.0mm
max9396 part number table english ? ? ?Z ? ??? what's new products solutions design appnotes support buy company members didn't find what you need? notes: 1. see the max9396 quickview data sheet for further information on this product family or download the max9396 full data sheet (pdf, 168kb). 2. other options and links for pu rchasing parts are listed at: http://www.maxim-ic.com/sales . 3. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 4. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free ; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 5. * some packages have variations, listed on the drawing. "pkgcode/v ariation" tells which variation the product uses. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max9396ehj+ sample buy tqfp;32 pin;5x5x1.0mm dwg: 21-0110b (pdf) use pkgcode/vari ation: h32+1 * -40c to +85c rohs/lead-free: yes materials analysis max9396ehj+t buy tqfp;32 pin;5x5x1.0mm dwg: 21-0110b (pdf) use pkgcode/vari ation: h32+1 * -40c to +85c rohs/lead-free: yes materials analysis contact us: send us an email copyright ? 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy pa g e 1 of 2 max9396 - part number table - maxim/dallas 31-jul-2007 mhtml:file://c:\temp\maxm\max9396ehj+.mht
pa g e 2 of 2 max9396 - part number table - maxim/dallas 31-jul-2007 mhtml:file://c:\temp\maxm\max9396ehj+.mht

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